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DM141
Version : A.012 Issue Date : 2004/04/09 File Name : SP-DM141-A.012.doc Total Pages : 16
8x2-Channels Constant Current LED Driver
9 7 1
SILICON TOUCH TECHNOLOGY INC.
9-7F-1, Prosperity Road I, Science Based Industrial Park, Hsin-Chu, Taiwan 300, R.O.C. Fax886-3-5645626 Tel886-3-5645656
SILICON TOUCH TECHNOLOGY INC.
DM141
DM141 8x2-Bit Constant Current LED Drivers
General Description
The DM141 is a constant current driver specifically designed for LED display applications. The device includes a 16-bit shift register, a latch, and dual-interleaved banks of constant current drivers on a single Silicon CMOS chip. Each of the dichotomous 8-bit banks requires a current setting resistor. The output current ranges from 5mA to 60mA.
Features
Constant Current Output: From 5mA to 60mA Maximum Clock Frequency: 25MHz (Max) Power Supply Voltage: 3.3V to 5.0V CMOS Compatible Input/Output Package: QFN32, SDIP28, SSOP28 Constant Current Matching: 10mA to 60mA 5mA to 10mA : Bit-to-Bit : 4.0% (Max) Chip-to-Chip : 10 .0% (Max) : Bit-to-Bit : 6.0% (Max)
Chip-to-Chip : 12 .0% (Max) Maximum Output Voltage: 17V Two-color LED driving capability on chip
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Pin Connection (Top view)
QFN32
GND
23
SDIP28, SSOP28
GND G6
24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 Thermal Pad GND
G4
G5
21
R3
R5
22
R4
20
19
18
R6 G7 R7 GND G8 R8 GND RESERVED
17 16 15 14 13 12 11 10 9
G3 R2 G2 GND R1 G1 GND EN
VDD SIN CLK LTH EN GND G1 R1 G2 R2 G3 R3 G4 R4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND RRES GRES SOUT RESERVED GND R8 G8 R7 G7 R6 G6 R5 G5
Pin Description
Pin No. (QFN32) 5 6 7 8 9 11, 14, 16, 19, 21, 24, 26, 29 12, 15, 17, 20, 22, 25, 27, 30 Pin No.
(SDIP28, SSOP28)
15,17,19,21 8,10,12,14, 16,18,20,22 Ground terminals. R1~8 Constant current output terminals (Bank R).
SOUT
1 2 3 4 5 7,9,11,13,
GRES
RRES
GND
Pin NAME
CLK LTH EN G1~8
VDD
SIN
CLK
LTH
FUNCTION
VDD SIN
Supply voltage terminal. Input terminal of a data shift register. Data for R8 should be shifted in first, and then the data for G8 followed. Input terminal of a clock for shift register. Data is sampled at the rising edge of CLK. Input terminal of data strobe. Data is latched when LTH is low. And data on shift register goes through when LTH is high. Input terminal of output enable (active low), all outputs are off when EN is high. Constant current output terminals (Bank G).
4, 10, 13, 18, 23, 28, 31 32 1 2 3
6,23,28
GND
24 25 26 27
RESERVED Reserved pin for future. SOUT GRES RRES Output terminal of a data shift register. Input terminal of an external resistor (Bank G). The current flows through the resistor from GRES to ground will be the (Bank G) reference base current of output sink current. Input terminal of an external resistor (Bank R).
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Block Diagram
G2
G3
G4
G5
G6
G7
G8
G1
R2
R3
R4
R5
R6
R7
15 En 16 En 14
13
11
09
07
05 04
03 02
01
R8
R1
EN
Bank B Constant Current Drivers 12 10 08 06 Bank A Constant Current Drivers
Bank R Current Controller Bank G Current Controller
RRES
GRES
LTH
16 Bit Latch
VDD GND
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
SIN SOUT
16 Bit Shift Register
CLK
Equivalent Circuit of Inputs and Outputs
1. CLK, SIN, LTH, EN terminals
2. SOUT terminal
VDD INPUT
VDD
SOUT GND
GND
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Maximum Ratings (Tj(max) = 150C)
CHARACTERISTIC Supply Voltage Input Voltage Output Current Output Voltage Clock Frequency GND Terminal Current Power Dissipation SYMBOL VDD VIN IOUT VOUT fCLK IGND PD RATING 0 ~ 7.0 -0.3 ~ VDD+0.3 60 -0.3 ~ 17 25 960 3.08 (QFN-32 : Ta=25C) 3.12 (SDIP-28 : Ta=25C) 1.1 (SSOP-28 : Ta=25C) 40.6 (QFN-32) Thermal Resistance Storage Temperature Rth(j-a) Tstg 40 (SDIP-28) 113.3 (SSOP-28) -40 ~ 150 C C/W W UNIT V V mA V MHz mA
Recommended Operating Condition
CHARACTERISTIC Supply Voltage Output Voltage Operating temperature Output Current SYMBOL VDD VOUT TOPR IO IOH IOL VIH VIL tw LAT tw CLK tsetup(D) thold(D) tsetup(L) fCLK CONDITION

(G, R)n SOUT SOUT
MIN. 3.0
TYP. 5.0
-20 5
Input Voltage LTH Pulse Width CLK Pulse Width Set-up Time for DATA Hold Time for DATA Set-up Time for LTH Clock Frequency

0.8VDD -0.3 15 15 10 10 15
VDD = 3.3 ~ 5.0 V
Cascade operation

MAX. 5.5 17 85 60 1.0 -1.0 VDD+0.3 0.2VDD
UNIT V V mA
V ns ns ns ns ns MHz

25
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DM141
Electrical Characteristics (Typ:VDD = 5.0 V, Ta = 25C unless otherwise noted)
CHARACTERISTIC Input Voltage "H" Level Input Voltage "L" Level Output Leakage Current Output Voltage (SOUT) SYMBOL VIH VIL IOH VOL VOH Output Current (Bit-Bit) IOL1 VOH = 17 V IOL = 1.0 mA IOH = -1.0 mA V(G, R)n = 1.0 RES = 11.2K V(G, R)n = 1.0V, Vdd=5.0V RES = 11.2K Vdd=3.3V CONDITION MIN. 0.8VDD GND VDD-0.3 4.66 4.57 TYP. 5.3 5.2 0.1 1.5 6 MAX. VDD 0.2VDD 1.0 0.3 6 5.94 5.83 0.5 3.0 %/V %/V uA V UNIT V
% mA
Output Current (Chip-Chip) Output Voltage Regulation Supply Voltage Regulation
IOL3
% / VDD RES = 1400, V(G, R)n = 1V to 3V % / VDD V(G, R)n = 1.0V, RES = 1400 IDD(off)1 Input Signal is static, RES = OPEN, (G, R)1~8 = off Input Signal is static, RES = 2800, (G, R) 1~8 = off Input Signal is static, RES = 1400, (G, R) 1~8 = off Input Signal is static, RES = 2800, (G, R) 1~8 = on Input Signal is static, RES = 1400, (G, R) 1~8 = on
Supply Current "OFF"
IDD(0ff)2
9.5
IDD(off)3
12.5
mA
IDD(on)1 Supply Current "ON" IDD(on)2
9.5
12.5
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DM141
Switching Characteristics (Ta = 25 C unless otherwise noted)
CHARACTERISTIC Propagation Delay Time ("L" to "H") Propagation Delay Time ("H" to "L") Output Current Rise Time Output Current Fall Time tor tof EN-(G, R)n tpHL EN-(G, R)n tpLH SYMBOL CONDITION VDD=5.0V VIH=VDD VIL=GND (G, R)RES=1400 VL=3.3V RL=51 CL=15pF 90 17 ns ns 30 ns 60 ns MIN. TYP. MAX. UNIT
CHARACTERISTIC Propagation Delay Time ("L" to "H") Propagation Delay Time ("H" to "L") Output Current Rise Time Output Current Fall Time EN-(G, R)n EN-(G, R)n
SYMBOL
CONDITION VDD=3.3V
MIN.
TYP.
MAX.
UNIT
tpLH
VIH=VDD VIL=GND (G, R)RES=1400
90
ns
tpHL
VL=3.3V RL=51 CL=15pF
35
ns
tor tof

140 30

ns ns
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DM141
Timing Diagram
1. CLK-SIN, SOUT, (G,R)n
tr twCLK
90% 50% 10% 90% 50% 10%
tf
twCLK
50% 50%
CLK
tsetup
thold
SIN
50%
50%
tor (G, R)n (current) tpLH
50% 90% 50% 10%
tof
90% 50% 10%
tpHL
50%
SOUT tpLH tpHL
2. CLK-LTH
50%
CLK
SIN
"L" level = DATA HOLD tw(LAT)
50% 50%
LTH
tsetup(L)
3. EN-(G, R)n
EN
50% 50%
tpLH
tpHL
50%
50%
(G, R)n (current)
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DM141
Detailed Description
Constant Current Output Value Setting
The output current is determined by resistor value. The resistors connected between RES(G, R) pin and GND decide the base current output. Fig1. shows the approximate relation between resistor value and output current value. The resistor should be placed as close to Rext terminal as possible to avoid the noise influence
60.00
50.00
40.00 Iout (mA)
30.00
20.00
10.00
0.00 0 2 4 6 8 Rext (KOhm) 10 12 14
Fig.1 Output Current Performance vs. Output Voltage
In order to obtain the good constant current output performance, the minimum output voltage is necessary.
60.00 50.00
Iout (mA)
40.00 30.00 20.00 10.00 0.00 0 1 2 3 4 5
Vout (V)
Fig. 2
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DM141
Serial_In Data, Serial_Out and Latch
The SIN data will be clocked into the 16 bits shift register synchronized on the rising edge of CLK. And the data `1' represents the corresponding current output `ON', while the data `0' stands for `OFF'. The data will be transferred into the latch as the LTH pin goes high. And the data will be latched when LTH goes low.The SERIAL_OUT data is shifted out on synchronization to the falling edge of CLOCK. The graph below depicts the timing of data serial-in and serial-out.
16 Clocks CLK SIN LTH EN SOUT G1 R1 G2 R2
5V 0V 5V 0V 5V 0V 5V 0V
Previous Data
5V 0V ON OFF ON OFF ON OFF ON OFF
R7 G8 R8
ON OFF ON OFF ON OFF
Package and Thermal Pad
The IC's thermal pad (QFN) which is internally connected to the bottom side of chip should be connected to GND. And, good PCB layout pattern conducted to thermal pad will have better performance in thermal effect. Due to the small size and low profile, the majority of heat generated by the die within this package is dissipated through the thermal pad to PCB. The PCB configuration and metal layers embedded in the PCB become important to achieving good thermal performance. By increasing the embedded copper area, the thermal performance will be improved. Thermal vias which conduct heat from the surface of the PCB to the ground plane are necessary. More vias may improve the package thermal performance.
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Typical Application
VDD
VLED A1 A2 A3 A4 A5 A6 A7
R-G Dual Color 8X8 LED Module
Controller
A8 VDD VDD 0.1 uF GND DM141 8x2 Channels Constant Current LED Driver GRES RRES To Next Stage
SIN CLK LTH EN
G1 R1 G2 R2 G3 R3 G4 R4 G5 R5 G6 R6 G7 R7 G8 R8
SOUT
8x2-Bit Constant Current LED Drivers
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DM141
Typical Application
VDD
0.1 uF GND GRES RRES SOUT
EN LTH CLK SIN VLED Controller
DM141 8x2 Channels Constant Current LED Driver
G2 G2 G2 G2 R2 R2 R2 R2
R2 G2
G3 G3 G3 G3 R3 R3 R3 R3
G4 G4 G4 G4 R4 R4 R4 R4
G5 G5 G5 R5
G6 R6
G7 R7
G8 R8 R8 R8 R8
R3 G3
R4 G4
R5 G5
R6 G6
R7 G7
SIN CLK LTH EN
R1 G1
DM141 8x2 Channels Constant Current LED Driver GND VDD 0.1 uF GRES RRES
R8 G8
8x2-Bit Constant Current LED Drivers
G1 R1 R1 R1 R1
R R
G B
Full-Color LED Pixel Cluster
SOUT
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DM141
Package Outline
QFN32
TOP VIEW
0.25 C
BOTTOM VIEW
D2
25 24 24 25 32 1
D
32 1
e
8 0.25 C 9 16
17
17
8 16 9
L
e
0.10 C
b
0.10
M
CAB
SEATING PLANE A3 A1
A
yC
SYMBOL A A1 A3 B D D2 E E2 e L y MIN. 0.70 0 0.18 1.25 1.25 0.30
DIMENSION (MM) NOM. 0.75 0.02 0.25 REF 0.23 5.00 BSC 2.70 5.00 BSC 2.70 0.50 BSC 0.40 0.10
MAX. 0.80 0.05 0.30 3.25 3.25 0.50
MIN. 27.6 0 7.09 49.21 49.21 11.81
DIMENSION (MIL) NOM. 29.5 0.79 9.84 REF 9.06 196.85 BSC 106.30 196.85 BSC 106.30 19.69 BSC 15.75 3.94
MAX. 31.5 1.97 11.81 127.95 127.95 19.69
Note: 1.DIMENSIONING AND TOLERANCING CONFORM TO ASME Y145.5M-1994. 2. REFER TO JEDEC STD. MO-220 WHHD-2 ISSUE A
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E2
E
SILICON TOUCH TECHNOLOGY INC.
DM141
Package Outline
SDIP28
D E1 A2 A SEATING PLANE A1 L 0.018typ. 0.060typ. 0.100typ.
SYMBOLS
A A1 A2 D E1 E L
eB
DIMENSION IN MIN. NOM. 0.015 0.125 0.130 1.385 1.390 0.283 0.288 0.31 BSC 0.115 0.130 0.330 0.350 0 7
INCH MAX. 0.210 0.135 1.400 0.293 0.150 0.370 15
Note: 1. JEDEC OUTLINE : N/A
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eB
E
SILICON TOUCH TECHNOLOGY INC.
DM141
Package Outline
SSOP28
D
DETAIL A E1 c C
0.25 MM
E
A2
R R L
DETAIL A
A
GAUGE PLANE SEATING PLANE
0.1MM
e
b
A1
SYMBOLS
NOTES: 1. JEDEC OUTLINE : MO-15D AH 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DOES INCLUDE MODE MISMATCH AND ARE MEASURED AT DATUM PLANE, MOLD PARTING LINE. MOLD FLASH OR PROTRUSION SHALL NOT EXCEED 0.2MM PER SIDE. 3.DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/ INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 9.07mm AT LEAST MATERIAL CONDITION.
A A1 A2 b C e D E E1 L R
DIMENSION IN MM MIN. NOM. MAX. 2.0 0.05 1.62 1.75 1.85 0.22 0.38 0.09 0.25 0.65 BSC 9.9 10.20 10.50 7.4 7.8 8.2 5.00 5.30 5.60 0.55 0.75 0.95 0.09 0 4 8
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The products listed herein are designed for ordinary electronic applications, such as electrical appliances, audio-visual equipment, communications devices and so on. Hence, it is advisable that the devices should not be used in medical instruments, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. Misusing those products may directly or indirectly endanger human life, or cause injury and property loss. Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage of the products mentioned above. Anyone who purchases any products described herein with the above-mentioned intention or with such misused applications should accept full responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all their officers and employees shall defend jointly and severally against any and all claims and litigation and all damages, cost and expenses associated with such intention and manipulation.
8x2-Bit Constant Current LED Drivers
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